1. Technical Field
The present invention generally relates to non-planar semiconductor device fabrication. More particularly, the present invention relates to reducing or eliminating non-uniform gate height in mixed n-type and p-type non-planar semiconductor device fabrication.
2. Background Information
As semiconductor device size continues to shrink, issues with the fabrication process arise and solutions are explored. For example, raised semiconductor structures (e.g., “fins”) allowed size to continue to be reduced versus planar structures. As another example, the use of dummy gates early in the fabrication of FinFETs, replaced later in the process with metal gates, along with the use of epitaxial semiconductor structures on the fins for the active regions, has further allowed for size reduction. However, in practice, when mixed non-planar n-type and p-type devices are co-fabricated on the same substrate, and a replacement metal gate process employed, masks used to protect each type device while operating on the other can sometimes overlap, creating a “bump” at the “boundary” of the masks. The bump can lead to problems with replacing the gate, as well as non-uniform gate height.
Therefore, a need exists for a way to reduce or eliminate non-uniform gate height due to an overlapping mask bump in mixed-type non-planar semiconductor device fabrication.